1. Technical Field
The present disclosure relates to non-volatile memories and more particularly to a sense amplifier for reading non-volatile memory cells.
2. Description of the Related Art
Sense amplifiers are conventionally used to detect a conductivity state of non-volatile memory cells, which may generally be a high-conductivity state or a low-conductivity state, and to supply a data signal which depends on the state of the memory cell. For example, the cells of electrically erasable and programmable memories may be in a programmed state or in an erased state which correspond to two different conductivities.
Sense amplifiers may be asymmetric or differential. Asymmetric sense amplifiers have an internal current source or a voltage source to detect, via a single detection input, the state of a memory cell. Differential sense amplifiers have two detection inputs. FIG. 1 represents an example of a conventional differential sense amplifier SA1, of the type described in U.S. Pat. No. 8,363,499. The sense amplifier SA1 has a first detection input SI1 and a second detection input S12. The first detection input SI1 is coupled to a memory cell MC through a bit line BL1. The second detection input SI2 is connected to a reference line BL2 coupled to a current source CS1 or to any other reference element such as a reference resistor.
The sense amplifier SA1 comprises a latch circuit LT1 comprising two inverter gates mounted head-to-tail IG1, IG2. One output of the gate IG1 and one input of the gate IG2 are connected to a first output node O1, and one output of the gate IG2 and one input of the gate IG1 are connected to a second output node O2. The node O1 supplies a logic data signal L and the node O2 supplies a logic data signal R. The inverter gate IG1 is powered by an enabling signal ENA through a first P-channel control transistor P3. The inverter gate IG2 is powered by the enabling signal ENA through a second P-channel control transistor P4. The enabling signal ENA is taken to a voltage Vcc (ENA=1) to enable the latch circuit LT1 and is put to the ground (ENA=0) to disable the latch circuit. The gate terminal (G) of the transistor P3 forms a first control input L2 of the latch circuit LT1 and is coupled to the first detection input SI1 of the sense amplifier SA1. The gate terminal (G) of the transistor P4 forms a second control input of the latch circuit and is coupled to the second detection input SI2 of the sense amplifier SA1.
The inverter gate IG1 comprises for example a P-channel transistor P1 and an N-channel transistor N1 having their drain terminals (D) connected to the output node O1 and their gate terminals (G) connected to the output node O2. The source terminal (S) of the transistor N1 is connected to the ground and the source terminal (S) of the transistor P1 is connected to the drain terminal (D) of the control transistor P3. Similarly, the inverter gate IG2 comprises a P-channel transistor P2 and an N-channel transistor N2 having their drain terminals (D) connected to the output node O2 and their gate terminals (G) connected to the output node O1. The source terminal (S) of the transistor N2 is connected to the ground and the source terminal (S) of the transistor P2 is connected to the drain terminal (D) of the control transistor P4.
The first control input L2 is coupled to the first detection input SI1 through an N-channel cascode transistor N5 and the second control input R2 of the latch circuit LT1 is coupled to the second detection input SI2 by an N-channel cascode transistor N6. The cascode transistors N5, N6 are controlled by a signal CLSC applied to their gate terminals (G). The sense amplifier SA1 further comprises P-channel precharge transistors P5, P6. Each precharge transistor P5, P6 has its drain terminal (D) connected to a control input of the latch circuit, respectively L2, R2, and receives the supply voltage Vcc on its source terminal (S), and a precharge signal PRE on its gate terminal (G). The sense amplifier SA1 also comprises a latch circuit CLC1. The latch circuit CLC1 comprises two N-channel transistors N7, N8. Each transistor N7, N8 has its drain terminal (D) connected to one of the detection inputs SI1, SI2 respectively, its source terminal (S) connected to the ground, and receives a latching signal CLP on its gate terminal (G). The latching signal CLP is supplied by an OR gate G1 which receives at input the first and second data signals L, R. Thus the latching signal CLP is automatically enabled when one of the first and second data signals L, R increases and reaches a threshold voltage.
The reading of the memory cell MC comprises a precharge phase and a reading phase. During the precharge phase, the two detection inputs SI1, SI2 are taken to a precharge voltage by means of the transistors P5, P6 and through the cascode transistors N5, N6. The voltage Vcc is applied to the source terminals (S) of the control transistors P3, P4 of the latch circuit LT1.
Once a precharge voltage has been reached on the bit line BL1 and on the reference line BL2, the precharge signal PRC is pulled up and the reading of the memory cell MC begins. The bit line BL1 and the reference line BL2 begin to discharge. The voltages INL, INR respectively present on the first and second detection inputs SI1, SI2 begin to decrease at different speeds, creating a voltage difference which depends on whether the memory cell is in the high- or low-conductivity state. If the memory cell MC is in the high-conductivity state, the voltage present on the bit line BL1 drops more rapidly than the voltage on the reference line BL2. If the memory cell is in the low-conductivity state, the voltage present on the bit line BL1 drops more slowly than the voltage on the reference line BL2. The voltage difference between the bit line BL1 and the reference line BL2 is amplified by the cascode transistors N5, N6 and supplied between the gate terminals of the control transistors P3, P4. The result is that the control transistor P3, P4 corresponding to the bit BL1 or reference BL2 line the voltage of which drops most rapidly becomes on, whereas the other control transistor remains off. The latch LT1 thus switches to one of its two possible states, and the sense amplifier SA1 supplies a data signal L=0 or L=1 corresponding to the conductivity state of the memory cell MC. The switch of the latch LT1 also has the effect of enabling the latching signal CLP, which renders the transistors N7, N8 on, and thus initializes the voltages on the bit line BL1 and the reference line BL2.
It transpires that this sense amplifier architecture does not support low supply voltages such as those available in low-voltage devices, powered by a battery or by a near field communication (NFC) interface circuit generating a supply voltage from a signal transmitted by inductive coupling and charge modulation.
It is thus desirable to propose a sense amplifier capable of functioning on a wide range of supply voltages, having a good immunity to noise, and a low current consumption. It is also desirable to propose a sense amplifier that rapidly and accurately reads a memory cell, particularly of a non-volatile memory.